1. Field of the Invention
This invention relates to devices for reproducing a digital signal, and more particularly, to a frame synchronizing signal detecting and compensating circuit for use in a reproducing apparatus which generates a digital signal separated into frames.
2. Description of the Prior Art
An audio signal can be digitally recorded on a disc by a pulse code demodulation (PCM) system. The audio PCM signal is recorded on a base band which is not the carrier modulation system (and can be, for example, amplitude modulation, frequency modulation, or the like.) A run length limited code has been used to record the audio PCM signal on the disc. In a run length limited code, a minimum transition interval T.sub.min extends between two pieces data in order to enhance the efficiency of the recording (where T.sub.min is the minimum number of consecutive bits of the same type.) A maximum transition interval T.sub.max between two data pieces is shortened so that the self clocking action performed by the reproducing apparatus is more easily performed (where T.sub.max is the maximum number of consecutive bits of the same type).
The digital signal is frequently separated into a number of blocks or frames so that error correction and other processing can be easily performed. Usually, each block of data is individually processed in the conversion to analog data. In a digital audio disc, the length of one data block is made equal to one frame period. Each data block, of course, is provided at its start point with a frame or block synchronizing signal.
A bit pattern not used in the run length limited code is ordinarily selected as the frame synchronizing signal for ease of detection. One prior art system takes advantage of the fact that the modulation output of two maximum transition intervals T.sub.max do not occur in the normal modulation method, and uses as the frame synchronizing signal a bit pattern of two successive maximum transition intervals T.sub.max. With respect to a run length limited code, this means that the frame synchronizing signal is formed by a first interval of continuous "1"s during the first maximum transition interval T.sub.max, followed by a second interval of continuous "0"s during the next maximum transition interval T.sub.max.
However, the frame synchronizing signal is not always properly detected and processed. Accordingly, a compensating circuit which compensates for an improperly detected and/or processed frame synchronizing signal is generally provided in the reproducing apparatus.
The compensating circuit in the reproducing apparatus must accommodate a number of different kinds of errors. For example, a frame synchronizing signal can be omitted or "dropped" by a scratch or the like formed on the surface of the disc. As another example, a pulse form which closely resembles the frame synchronizing signal can occur in a reproduced signal. Such a digital signal can be erroneously identified as a frame synchronizing signal, with the result that subsequent data processing operations are erroneously performed. As a third example, when a digital audio disc player is operated in a search mode to access the beginning of an audio signal, the frame synchronizing signal might not be detected. It is preferable for the frame synchronizing signal to be immediately identified upon the completion of the search mode, so that the audio signal can be correctly reproduced in the normal playback mode. As a fourth example, the frame period for the digital data can vary.
Conventional compensating circuits for use in reproducing apparatuses require a memory which operates at high speed. A majority logic circuit is also used to identify the frame synchronizing signals. In such a majority logic circuit, when a doubtful frame synchronizing pulse occurs repeatedly at the same position in each frame period, the doubtful frame synchronizing pulses cannot be removed.
Reproducing apparatuses for digitally recorded signals generally employ a control circuit to control the rotational speed of the disc. A velocity control circuit controls large fluctuations in the speed of the disc. A phase control circuit controls minor fluctuations in the speed of the disc since it has a limited lock range. The phase control circuit thus cannot be locked into operation until the speed of the disc is approximately set by the velocity control circuit. Accordingly, the speed of the disc must be ascertained before the phase control circuit is switched into operation with the velocity control circuit.